学者信息
已发表成果：
WOK 论文 4 篇;其它论文 1 篇;专利发明 2 个;
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High-throughput and area-efficient fully-pipelined hashing cores using BRAM in FPGA
Microprocessors and Microsystems,0141-9331,2019-06.
Li, Lin (1); Lin, Shaoyu (1); Shen, Shuli (1); Wu, Kongcheng (1); Li, Xiaochao (1, 2); Chen, Yihui ...
WOS:000466250500008 EI:20191306691074 10.1016/j.micpro.2019.03.002
收录情况：SCIE、EI -
A High Throughput and Pipelined Implementation of the LUKS on FPGA
Journal of Circuits, Systems and Computers,0218-1266,2019.
Li, Xiaochao; Wu, Kongcheng; Zhang, Qi; Lin, Shaoyu; Chen, Yihui; Wong, Shen Yuong
WOS:000537364400010 EI:20192907210460 10.1142/S0218126620500759
收录情况：SCIE、EI